The present invention generally relates to the control of a power MOS transistor or other power component having a high input capacitance.
This input capacitance has a non negligible effect since such devices are usually used for switching operation and switching frequencies are increasing to higher and higher values.
FIGS. 1A and 1B are circuit diagrams of two variants of an elementary switching circuit for a power MOS transistor T. In the case represented, the transistor T has a source connected to ground M and a drain connected directly or indirectly to a load to switch electric energy thereto. Transistor T exhibits a gate/source capacitance C.sub.gs and a gate/drain capacitance generally called "Miller capacitance" C.sub.m. If it is desired to rapidly switch transistor T, it is necessary to rapidly load and unload the input capacitance C.sub.e equivalent to capacitances C.sub.m and C.sub.gs. For this purpose, circuits exhibiting the features illustrated in FIG. 1A or 1B are used.
The gate G of transistor T can be connected either to a supply terminal 10 (voltage V) or to ground M respectively through switches 11 and 12. However, this connection generally exhibits a series resistor which can be either, as in the case of FIG. 1A, connected between the tap of the switches and the gate, or, as in the case of FIG. 1B, in series with each switch 11 and 12. For each switching operation, energy CV.sup.2 /2 is dissipated in each corresponding resistor (this energy does not depend upon the resistance but only upon the gate capacitance and the applied voltage). If the frequency becomes very high, a high number of switching events occur every second (a million at one megahertz) and this loss of energy is no longer negligible. If the input capacitance has a value of 10 nF and the input voltage a value of 15 volts, the power consumed for each switching event is 1.13 .mu.J, that is, an energy consumption of 1.13 J/s at 1 MHz.
It is already known to make circuits wherein there is an inductance in series with the gate of the transistor it is desired to control. However, this series inductance is coupled through a resistor to an inductance having a value L associated with a load transformer. This arrangement shifts the phase of the transistor control with respect to the current in the main load circuit. In those circuits there is a dissipation of about CV.sup.2 /2 during each switching operation. Moreover, those circuits do not permit modification of the switching frequency since the latter is associated with the circuit resonance frequency and therefore depends upon the values of the chosen inductances and capacitors.
Thus, an object of the invention is to provide a new and improved low dissipation gate control circuit for a power MOS transistor.
Another object of the invention is to provide a new and improved gate control circuit for a power MOS transistor with a voltage higher than the voltage of the supply source.
A further object of the invention is to provide a new and improved switching circuit that can operate over a wide range of switching frequencies.